Abstract. Two models of logic circuit are proposed for Mealy FSM. The models target on FPGA with embedded memory blocks and are based on transformation of the object codes. To decrease the number of LUT elements, it is proposed to decrease the number of irregular functions representing FSM. Both example of design and results of experiments are given for the method based on transformation of the codes of collections of microoperations into state codes of FSM. Figs: 7. Tabl.: 6. Refs: 15 titles.

Keywords: microprogrammed Mealy FSM, FPGA, structural decomposition, embedded memory blocks.