УДК 004.274

О.О. БАРКАЛОВ
Університет Зеленогурський, Зелена Гура, Польща,  A.Barkalov@iie.uz.zgora.pl

Л.О. ТІТАРЕНКО
Університет Зеленогурський, Зелена Гура, Польща; Харківський національний університет радіоелектроніки, Харків, Україна,  L.Titarenko@iie.uz.zgora.pl

О.М. ГОЛОВІН
Інститут кібернетики ім. В.М. Глушкова НАН України, Київ, Україна,
 o.m.golovin.1@gmail.com

О.В. МАТВІЄНКО
Інститут кібернетики ім. В.М. Глушкова НАН України, Київ, Україна,
 avmatv@ukr.net

ОПТИМІЗАЦІЯ СХЕМИ АВТОМАТА MІЛІ
У ЗМІШАНОМУ ЕЛЕМЕНТНОМУ БАЗИСІ

СПИСОК ЛІТЕРАТУРИ

1. Sklyarov V., Skliarova I., Barkalov A., Titarenko L. Synthesis and optimization of FPGA-based systems. Berlin: Springer, 2014. 432 p.


2. Czerwinski R., Kania D. Finite state machines logic synthesis for complex programmable logic devices. Berlin: Springer, 2013. 172 p.


3. Kubica M., Opara A., Kania D. Technology mapping for LUT-based FPGA. Cham: Springer, 2021. 207 p. doi.org/10.1007/978-3-030-60488-2 .


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6. BarkalovA., Titarenko L., Mielcarek K., Chmielewski S. Logic synthesis for FPGA-based control units. Lecture Notes in Electrical Egineering. 2020. Vol. 636. 247 p.


7. Tiwari A., Tomko K. Saving power by mapping finite state machines into embedded memory blocks in FPGAs. Proc. Design, Automation and Test in Europe Conference and Exhibition (6–20 Feb, 2004, Paris, France). 2004. Vol. 2. P. 916–921.


8. Senhaji-Navarro R., Garcia-Vargas I., Jimenes-Moreno G., Civit-Balcells A., Guerra-Gutierres P. ROM-based FSM implementation using input multiplexing in FPGA devices. Electronics Letters. 2004.Vol. 40, N 20. Р. 1249–1251.


9. Grout I. Digital systems design with FPGAs and CPLDs. Amsterdam: Elsevier, 2008. 784 p.


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13. Barkalov A., Titarenko L., Mielcarek K. Improving characteristics of LUT-based Мealy FSMs. International Journal of Applied Mathematics and Computer Science. 2020. Vol. 30, N 4. P. 745–759.


14. Barkalov A., Titarenko L., Mielcarek K. Hardware reduction for LUT-based Mealy FSMs. International Journal of Applied Mathematics and Computer Science. 2018. Vol. 28, N 3. Р. 595–607.


15. Barkalov A.A., Titarenko L.A., Barkalov A.A., Jr. A structural decomposition as a tool for the optimization of an FPGA-based implementation of a Мealy FSM. Cybernetics and Systems Analysis. 2012. Vol. 48, N 2. P. 313–322. doi.org/10.1007/s10559-012-9410-2 .


16. Skliarova I., Sklyarov V., Sudnitson A. Design of FPGA-based circuits using hierarchical finite state machines. Tallinn: TUT Press, 2012. 240 p.


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20. VC709 Evaluation Board for the Virtex-7 FPGA. User Guide; UG887 (v1.6); Xilinx, Inc.: San Jose, CA, USA, 2019.


21. Rafla N.I., Gauba I. A Reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM. 53rd IEEE International Midwest Symposium on Circuits and Systems. 2010. Р. 49–52.


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23. Kubica M., Kania D. Area-oriented technology mapping for LUT-based logic blocks. International Journal of Applied Mathematics and Computer Science. 2017. Vol. 27(1). Р. 207–222.


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26. Machado L., Cortadella J. Support-reducing decomposition for FPGA mapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2020. Vol. 39, N 1. P. 213–224.


27. Баркалов А.А., Титаренко Л.А. Преобразование кодов в композиционных микропрограммных устройствах управления. Кибернетика и системный анализ. 2011. № 5. C. 107–118.


28. Баркалов А.А., Титаренко Л.А., Ефименко К.Н. Оптимизация схем композиционных микропрограммных устройств управления. Кибернетика и системный анализ. 2011. № 1. C. 179–188.


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30. Barkalov A.A., Titarenko L.A., Baiev A.V., Matviienko A.V. Optimizing the combined automation schemein the asis basis. Cybernetics and Systems Analysis. 2020. Vol. 56, N 6. P. 863–871. doi.org/10.1007/s10559-020-00306-w .


31. Kryvyi S.L., Opanasenko V.N., Zavyalov S.B. Logical оperations over fuzzy sets and relations in automaton interpretation. Cybernetics and Systems Analysis. 2020. Vol. 56, N 6. P. 1012–1020. doi.org/10.1007/s10559-020-00321-x .