Abstract. A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.

Keywords: flowchart of algorithm, control unit, compositional microprogram control unit, code sharing, programmable logic devices of CPLD type, addressing of microcommands.